(1) Field of the Invention
This invention relates to semiconductor devices. It is particularly concerned with high breakdown voltage semiconductor devices.
Specifically, it relates to a semiconductor device having an improved breakdown voltage achieved by preventing excessive electric field concentrations at high curvature portions of the main junctions.
(2) Description of the Prior Art
Semiconductor devices with a high breakdown voltage were conventionally obtained by utilizing what is known as a mesa structure or a planar structure having a guard ring. The first structure has the advantage that (if the device is a diode) the PN junction, or (if the device is a transistor) the junction between base and collector are flat, so electric field concentrations do not occur. It is therefore widely used for semiconductor devices of high breakdown voltage.
However, with a mesa type structure, not only is it necessary to form a mesa to obtain the high breakdown voltage, but in addition the mesa has to be covered with a protective material. This complicates the manufacturing process. Semiconductor devices of planar structure having a guard ring are therefore often used, because they can be easily obtained by a simple manufacturing process. However, also in the case of planar semiconductor devices with a guard ring, if high breakdown voltages (1 KV or more, for example) are to be obtained, as many guard ring regions must be formed as possible, so as to raise the breakdown voltage by reducing the electric field concentration at the portions of high curvature of the PN junction (in the case of a diode) or the base-collector junction (in the case of a transistor). This made it difficult to reduce the element size.
Moreover, particularly with recent progress in CVD techniques, forming high-resistance materials such as polysilicon has become easier, and the so-called "resistive field plate" method has attracted attention, in which a high-resistance layer is provided on top of a dielectric arranged on the peripheral surface of a PN junction. Compared with use of a guard ring, this resistive field plate method has the advantages that only a comparatively small area is needed, the breakdown voltage dependence on junction depth is small and it is not so dependent on the accuracy of the transverse spread of the junction as the guard ring method is on the accuracy of the separation from the guard ring junction. However, neither this method nor the guard ring method enable electric field concentrations at curved portions of the PN junction to be relieved as effectively as they can be with the mesa structure.
U.S. Pat. No. 3,717,515 discloses a method for fabricating a monolithic integrated circuit including at least one pedestal transistor device in order to enable the formation of transistor devices having smaller dimensions than previously without sacrificing high frequency switching performance.